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| TC1270A/70AN/71A Voltage Supervisor with Manual Reset Input Features: * Precision voltage monitor - 2.63V, 2.93V, 3.08V, 4.38V and 4.63V trip points (Typical) * Manual Reset input * Reset Time-out Delay: - Standard: 280 ms (Typical) - Optional: 2.19 ms, and 35 ms (Typical) * Power Consumption 15 A max * No glitches on outputs during power-up * Active Low Output Options: - Push-Pull Output and Open-Drain Output * Active High Output Option: - Push-Pull Output * Replacement for (Specification compatible with): - TC1270, TC1271 - TCM811, TCM812 * Fully static design * Low voltage operation (1.0V) * ESD protection: - 4 kV Human Body Model (HBM) - 400V Machine Model (MM) * Extended (E) Temperature range: -40C to +125C * Package Options: - 4-lead SOT-143 - 5-lead SOT-23 - Pb-free Device Package Types SOT-143 VSS 1 4 VDD VSS TC1270A SOT-143 1 4 VDD TC1271A RST 2 3 MR RST 2 3 MR SOT-23-5 NC VDD MR 1 2 3 5 VSS NC VDD 4 RST MR TC1270A TC1270AN SOT-23-5 1 2 3 5 VSS TC1271A 4 RST Functional Block Diagram VDD Voltage Detector Circuitry Reset Generator & Delay Timer (2.19 ms, 35 ms, 280 ms) RST (TC1271A) RST PP (TC1270A) RST OD (TC1270AN) PP Output Driver Comment DS22035B-page 1 18.5 k MR Glitch Filter Device Features Reset Delay (ms) (Typ)(3) Reset Trip Point (V) (3) Voltage Range (V) Output Device Type TC1270A Push-Pull Active Level Low Low High 2.19, 35, 280 (1) 4.63, 4.38, 3.08, 2.93, 2.63(4) 1.0V to 5.5V Temperature Range Packages TC1270AN Open-Drain TC1271A Note 1: 2: 3: 4: Push-Pull -40C SOT-23-5 New Option to +125C SOT-143 (2), Replaces TC1271 and SOT-23-5 TCM812 SOT-143 (2), Replaces TC1270 and SOT-23-5 TCM811 The 280 ms Reset Delay time-out is compatible with the TC1270, TC1271, TCM811, and TCM812 devices. The SOT-143 package is compatible with the TC1270, TC1271, TCM811, and TCM812 devices. Custom Reset Trip Points and Reset Delays available, contact factory. The TC1270/1 and TCM811/12 1.75V Trip Point Option is not supported. (c) 2007 Microchip Technology Inc. TC1270A/70AN/71A 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Supply Voltage (VDD to VSS) ...............................+7.0V Input Current, VDD ..............................................10 mA Output Current, RESET, RESET ........................10 mA Voltage on all inputs and outputs w.r.t. VSS ............................ -0.6V to (VDD + 1.0V) Storage Temperature Range ..............-65C to +150C Operating Temperature Range...........-40C to +125C Maximum Junction Temperature, TS ................... 150C ESD protection on all pins Human Body Model ....................................... 4 kV Machine Model .............................................. 400V Notice: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress ratings only and functional operation of the device at those or any other conditions above those indicated in the operational listing of this specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise noted, VDD = 5V for L/M versions, VDD = 3.3V for T/S versions, VDD = 3V for R version, TA = -40C to +125C. Typical values are at TA = +25C. Parameter Operating Voltage Range Supply Current Sym VDD IDD Min 1.0 -- -- -- Reset Trip Point Threshold (3) VTRIP 4.54 4.50 4.30 4.25 3.03 3.00 2.88 2.85 2.72 2.70 2.58 2.55 Note 1: 2: 3: 4: 5: 6: Typ(1) -- 7 4.75 10 4.63 -- 4.38 -- 3.08 -- 2.93 -- 2.77 -- 2.63 -- Max 5.5 15 10 15 4.72 4.75 4.46 4.50 3.14 3.15 2.98 3.00 2.82 2.85 2.68 2.70 Units V A A A V V V V V V V V V V V V VDD > VTRIP, for L/M/R/S/T, VDD = 5.5V VDD > VTRIP, for R/S/T, VDD = 3.6V VDD < VTRIP, for L/M/R/S/T TC127xAL: TA = +25C TA = -40C to +125C TC127xAM: TA = +25C TA = -40C to +125C TC127xAT: TA = +25C TA = -40C to +125C TC127xAS: TA = +25C TA = -40C to +125C TC127xA:(5) TA = +25C TA = -40C to +125C TC127xAR: TA = +25C TA = -40C to +125C Test Conditions Data in the Typical ("Typ") column is at 5V, +25C, unless otherwise stated. RST output for TC1270A, and TC1270AN, RST output for TC1271A. TC127XA refers to either the TC1270A, TC1270AN or TC1271A device. Hysteresis is within the VTRIP(MIN) to VTRIP(MAX) window. Custom ordered Voltage Trip Point. Minimum order volume requirement. This specification allows this device to be used in PIC(R) microcontroller applications that require the In-Circuit Serial ProgrammingTM (ICSPTM) feature (see device-specific programming specifications for voltage requirements). The total time that the RST pin can be above the maximum device operational voltage (5.5V) is 100s. Current into the RST pin should be limited to 2 mA. It is recommended that the device operational temperature be maintained between 0C to +70C (+25C preferred). For additional information, refer to Figure 2-41. DS22035B-page 2 (c) 2007 Microchip Technology Inc. TC1270A/70AN/71A ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise noted, VDD = 5V for L/M versions, VDD = 3.3V for T/S versions, VDD = 3V for R version, TA = -40C to +125C. Typical values are at TA = +25C. Parameter Reset Threshold Tempco Reset Trip Point Hysteresis (4) MR Input High Threshold MR Input Low Threshold MR Pull-up Resistance Open-Drain High Voltage on Output VODH VHYS VIH VIL Sym Min -- -- 2.3 0.7 VDD -- -- 10 -- Typ(1) 30 0.3 -- -- -- -- 18.5 -- Max -- -- -- -- 0.8 0.25 VDD 40 13.5 Units ppm/C % V V V V k V Open-Drain Output pin only. VDD = 3.0V, Time voltage > 5.5 applied 100s. Current into pin limited to 2 mA +25C operation recommended (Note 6) R/S/T only, ISINK = 1.2 mA, VDD = VTRIP(MIN) R/S/T only, ISINK = 1.2 mA, VDD = VTRIP(MAX) L/M only, ISINK = 3.2 mA, VDD = VTRIP(MIN) L/M only, ISINK = 3.2 mA, VDD = VTRIP(MAX) L/M only, ISINK = 50 A, VDD > 1.0V R/S/T only, ISOURCE = 500 A, VDD = VTRIP(MAX) L/M only, ISOURCE = 800 A, VDD = VTRIP(MAX) ISOURCE = 500 A, VDD VTRIP(MIN) VPIN = VDD Open-Drain configuration only. Percentage of VTRIP Voltage VDD > VTRIP(MAX), L/M only VDD > VTRIP(MAX), R/S/T only VDD > VTRIP(MAX), L/M only VDD > VTRIP(MAX), R/S/T only Test Conditions Reset Output Voltage Low (2) TC1270A/ TC1270AN TC1271A TC1270A/ TC1270AN TC1271A TC1270A/ TC1270AN VOL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.3 0.3 0.4 0.3 0.3 -- -- -- 1 1 50 V V V V V V V V A A pF Reset Output Voltage High (2) TC1270A TC1270A TC1271A VOH 0.8 VDD VDD - 1.5 0.8 VDD Input Leakage Current Open-Drain RST Output Leakage Capacitive Loading Specification on Output Pins Note 1: 2: 3: 4: 5: 6: IIL IOLOD CIO -- -- -- Data in the Typical ("Typ") column is at 5V, +25C, unless otherwise stated. RST output for TC1270A, and TC1270AN, RST output for TC1271A. TC127XA refers to either the TC1270A, TC1270AN or TC1271A device. Hysteresis is within the VTRIP(MIN) to VTRIP(MAX) window. Custom ordered Voltage Trip Point. Minimum order volume requirement. This specification allows this device to be used in PIC(R) microcontroller applications that require the In-Circuit Serial ProgrammingTM (ICSPTM) feature (see device-specific programming specifications for voltage requirements). The total time that the RST pin can be above the maximum device operational voltage (5.5V) is 100s. Current into the RST pin should be limited to 2 mA. It is recommended that the device operational temperature be maintained between 0C to +70C (+25C preferred). For additional information, refer to Figure 2-41. (c) 2007 Microchip Technology Inc. DS22035B-page 3 TC1270A/70AN/71A 1.1 1.1.1 AC CHARACTERISTICS TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS T F Frequency E Error Lowercase letters (pp) and their meanings: pp io Input or Output pin rx Receive bitclk RX/TX BITCLK drt Device Reset Timer Uppercase letters and their meanings: S F Fall H High I Invalid (High-impedance) L Low 2. TppS T Time osc tx RST Oscillator Transmit Reset P R V Z Period Rise Valid High-impedance FIGURE 1-1: TEST LOAD CONDITIONS Pin VSS CL = 50 pF DS22035B-page 4 (c) 2007 Microchip Technology Inc. TC1270A/70AN/71A 1.1.2 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 1-2: MR MR PIN AND RESET PIN WAVEFORM tMR tMRNI tRST tMD RST RST FIGURE 1-3: VTRIP(MIN) VDD 1V DEVICE VOLTAGE AND RESET PIN (ACTIVE LOW) WAVEFORM VTRIP VTRIP(MAX) tRST tRD tRST RST(1) RST VDD < 1V is outside the device operating specification. The RST (or RST) output state is unknown while VDD < 1V. Note 1: The TC1270AN requires an external pull-up resistor. TABLE 1-1: RESET AND DEVICE RESET TIMER REQUIREMENTS Electrical Characteristics: Unless otherwise noted, VDD = 5V for L/M versions, VDD = 3.3V for T/S versions, VDD = 3V for R version, TA = -40C to +125C. Typical values are at TA = +25C. Parameter VDD to Reset Delay Reset Active Timeout Period TC127XAxBVyy (3) TC127XAxCVyy (3) TC127XAxVyy (3) Sym tRD tRST Min -- 1.09 17.5 140 Typ(1) 50 2.19 35 280 -- 0.1 0.2 Max -- 4.38 70 560 -- -- -- Units s ms ms ms s s s Test Conditions VDD = VTRIP(MAX) to VTRIP(MIN) -125 mV VDD = VTRIP(MAX) VDD = VTRIP(MAX) VDD = VTRIP(MAX) MR Minimum Pulse Width MR Noise Immunity MR to Reset Propagation Delay Note 1: 2: 3: tMR tMRNI tMD 10 -- -- Unless otherwise stated, data in the Typical ("Typ") column is at 5V, +25C. RST output for TC1270A, RST output for TC1271A. TC127XA refers to either the TC1270A, TC1270AN or TC1271A device. "x" indicated the selected Voltage Trip Point, while "yy" indicates the package code. (c) 2007 Microchip Technology Inc. DS22035B-page 5 TC1270A/70AN/71A TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +1.0V to +5.5V, VSS = GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 5L-SOT-23 Thermal Resistance, 4L-SOT-143 JA JA -- -- 256 426 -- -- C/W C/W TA TA TA -40 -40 -65 -- -- -- +125 +125 +150 C C C Sym Min Typ Max Units Conditions DS22035B-page 6 (c) 2007 Microchip Technology Inc. TC1270A/70AN/71A 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = -40C to +125C. 2.5 5.0V 7 6.5 4.0V 5.5V 2 IDD (A) 1.5 1 2.0V IDD (A) 3.0V 6 4.8V 5.5 5 4.5 0.5 0 -40 -20 0 20 40 60 80 1.0V 100 120 0 20 40 60 -40 -20 80 100 100 100 Temperature (C) Temperature (C) FIGURE 2-1: IDD vs. Temperature (Reset Power-up Timer Inactive) (TC1270AL, TC1270ANL, TC1271AL - 4.50V min. / 4.63V typ. / 4.75V max.). 3 2.5 IDD (A) 2 1.5 1 0.5 0 0 20 40 60 80 100 120 -40 -20 2.0V 1.0V 5.0V 4.0V 3.0V FIGURE 2-4: IDD vs. Temperature (Reset Power-up Timer Active) (TC1270AL, TC1270ANL, TC1271AL - 4.50V min. / 4.63V typ. / 4.75V max.). 7 6.5 6 IDD (A) 5.5 5 4.5 4 3.5 3 0 20 40 60 -40 -20 80 120 120 3.5V 5.5V 4.5V Temperature (C) Temperature (C) FIGURE 2-2: IDD vs. Temperature (Reset Power-up Timer Inactive) (TC1270AT, TC1270ANT, TC1271AT - 3.00V min. / 3.08V typ. / 3.15V max.). 3 5.0V FIGURE 2-5: IDD vs. Temperature (Reset Power-up Timer Active) (TC1270AT, TC1270ANT, TC1271AT - 3.00V min. / 3.08V typ. / 3.15V max.). 6.5 6 5.5 IDD (A) 5 4.5 4 3.5 3 2.5 0 20 40 60 -40 3.0V 4.0V 5.0V 2.5 4.0V IDD (A) 2 3.0V 1.5 1 0.5 0 0 20 40 60 80 100 120 -40 -20 2.0V 1.0V -20 Temperature (C) Temperature (C) FIGURE 2-3: IDD vs. Temperature (Reset Power-up Timer Inactive) (TC1270AR, TC1270ANR, TC1271AR - 2.55V min. / 2.63V typ. / 2.70V max.). (c) 2007 Microchip Technology Inc. FIGURE 2-6: IDD vs. Temperature (Reset Power-up Timer Active) (TC1270AR, TC1270ANR, TC1271AR - 2.55V min. / 2.63V typ. / 2.70V max.). DS22035B-page 7 80 120 TC1270A/70AN/71A Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = -40C to +125C. 3 2.5 IDD (A) 2 1.5 1 0.5 0 1 2 3 VDD (V) 4 5 -40C +125C 7 6.5 +25C +125C IDD (A) 6 5.5 -40C +25C 5 4.5 4.5 4.7 4.9 VDD (V) 5.1 5.3 5.5 FIGURE 2-7: IDD vs. VDD (Reset Power-up Timer Inactive) (TC1270AL, TC1270ANL, TC1271AL - 4.50V min. / 4.63V typ. / 4.75V max.). 3 2.5 2 IDD (A) 1.5 1 0.5 0 1 2 3 VDD (V) 4 5 -40C +125C +25C FIGURE 2-10: IDD vs. VDD (Reset Power-up Timer Active) (TC1270AL, TC1270ANL, TC1271AL - 4.50V min. / 4.63V typ. / 4.75V max.). 7 6.5 6 5.5 5 4.5 4 3.5 3 2.5 3 3.5 4 IDD (A) +125C +25C -40C 4.5 VDD (V) 5 5.5 FIGURE 2-8: IDD vs. VDD (Reset Power-up Timer Inactive) (TC1270AT, TC1270ANT, TC1271AT - 3.00V min. / 3.08V typ. / 3.15V max.). 3.5 3 2.5 IDD (A) 2 1.5 1 0.5 0 1 2 3 VDD (V) 4 5 -40C +125C +25C FIGURE 2-11: IDD vs. VDD (Reset Power-up Timer Active) (TC1270AT, TC1270ANT, TC1271AT - 3.00V min. / 3.08V typ. / 3.15V max.). 7 6 IDD (A) 5 4 3 2 2.5 3 3.5 4 VDD (V) 4.5 5 5.5 -40C +125C +25C FIGURE 2-9: IDD vs. VDD (Reset Power-up Timer Inactive) (TC1270AR, TC1270ANR, TC1271AR - 2.55V min. / 2.63V typ. / 2.70V max.). FIGURE 2-12: IDD vs. VDD (Reset Power-up Timer Active) (TC1270AR, TC1270ANR, TC1271AR - 2.55V min. / 2.63V typ. / 2.70V max.). DS22035B-page 8 (c) 2007 Microchip Technology Inc. TC1270A/70AN/71A Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = -40C to +125C. 4.65 4.645 4.64 4.635 4.63 4.625 4.62 4.615 4.61 4.605 0.4 0.38 0.36 0.34 0.32 0.3 0.28 0.26 0.24 0.22 0.2 125 0.12 0.1 3.0V 4.3V 2.0V 4.4V 4.5V VTRIP (with VDD Rising) VTRIP (V) VHYS (%) 0.08 VOL (V) 0.06 0.04 0.02 0 0.00 VHYS VTRIP (with VDD Falling) -40 25 Temperature (C) 1.00 2.00 IOL (mA) 3.00 4.00 FIGURE 2-13: VTRIP and VHYS vs. Temperature (TC1270AL, TC1270ANL, TC1271AL - 4.50V min. / 4.63V typ. / 4.75V max.). 3.086 3.084 3.082 3.08 3.078 3.076 3.074 3.072 3.07 3.068 3.066 -40 0.4 0.38 0.36 0.34 0.32 0.3 0.28 0.26 0.24 0.22 0.2 FIGURE 2-16: VOL vs. IOL (TC1270AL, TC1270ANL, TC1271AL - 4.50V min. / 4.63V typ. / 4.75V max.). 0.25 0.2 VHYS (%) 3.2V 3.15 4.0V VTRIP (with VDD Rising) VTRIP (V) VHYS VTRIP (with VDD Falling) VOL (V) 0.15 0.1 4.5V 5.0V 5.5V 0.05 0 0 2 25 Temperature (C) 125 4 IOL (mA) 6 8 FIGURE 2-14: VTRIP and VHYS vs. Temperature (TC1270AT, TC1270ANT, TC1271AT - 3.00V min. / 3.08V typ. / 3.15V max.). 2.64 2.635 VTRIP (V) VTRIP (with VDD Rising) FIGURE 2-17: VOL vs. IOL (TC1270AT, TC1270ANT, TC1271AT - 3.00V min. / 3.08V typ. / 3.15V max.). 2.625 2.62 2.615 2.61 -40 25 Temperature (C) 125 VHYS VTRIP (with VDD Falling) VHYS (%) VOL (V) 2.63 0.4 0.38 0.36 0.34 0.32 0.3 0.28 0.26 0.24 0.22 0.2 0.2 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 0 1 2 IOL (mA) 2.0V 2.45V 2.5V 3 4 FIGURE 2-15: VTRIP and VHYST vs. Temperature (TC1270AR, TC1270ANR, TC1271AR - 2.55V min. / 2.63V typ. / 2.70V max.). FIGURE 2-18: VOL vs. IOL (TC1270AR, TC1270ANR, TC1271AR - 2.55V min. / 2.63V typ. / 2.70V max.). (c) 2007 Microchip Technology Inc. DS22035B-page 9 TC1270A/70AN/71A Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = -40C to +125C. 0.12 0.1 VOL (V) VOH (V) 0.08 0.06 0.04 0.02 0 -40 10 60 110 Temperature (C) 0.2 A 1 mA 0.5 4 mA 2 mA 5.6 5.4 5.2 5 4.8 4.6 4.4 4.2 0.00 1.00 4.75V 4.8V 5.0V 5.5V 0.35 mA 2.00 3.00 4.00 5.00 IOH (mA) FIGURE 2-19: VOL vs. Temperature (TC1270AL, TC1270ANL, TC1271AL - 4.50V min. / 4.63V typ. / 4.75V max.). @ VDD = 4.5V). 0.35 0.3 0.25 VOL (V) 0.2 0.15 0.1 0.05 0 -40 10 60 110 Temperature (C) 4 mA 2 mA 1 mA 0.5 A 8 mA FIGURE 2-22: VOH vs. IOL (TC1270AL, TC1270ANL, TC1271AL - 4.50V min. / 4.63V typ. / 4.75V max.) @ +25C). 2.9 2.7 VOH (V) 6 mA 2.9V 2.7V 2.5 2.3 2.5V 2.1 1.9 1.7 0 1 2 3 4 5 IOH (mA) FIGURE 2-20: VOL vs. Temperature (TC1270AT, TC1270ANT, TC1271AT - 3.00V min. / 3.08V typ. / 3.15V max.). @ VDD = 2.7V). 0.2 0.15 VOL (V) 0.1 0.05 0 -40 10 60 110 Temperature (C) 0.2 A 1 mA 0.5 4 mA FIGURE 2-23: VOH vs. IOH (TC1270AT, TC1270ANT, TC1271AT - 3.00V min. / 3.08V typ. / 3.15V max.) @ +25C). 6 5.5 5 VOH (V) 4.5 4 3.5 3 2.5 2 0 1 2 IOH (mA) 3 4 5 2.8V 3.0V 5.5V 5.0V 4.5V 4.0V 2 mA 0.35 mA FIGURE 2-21: VOL vs. Temperature (TC1270AR, TC1270ANR, TC1271AR - 2.55V min. / 2.63V typ. / 2.70V max.). @ VDD = 1.8V). FIGURE 2-24: VOH vs. IOH (TC1270AR, TC1270ANR, TC1271AR - 2.55V min. / 2.63V typ. / 2.70V max.) @ +25C). DS22035B-page 10 (c) 2007 Microchip Technology Inc. TC1270A/70AN/71A Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = -40C to +125C. 55 54 53 52 51 50 49 48 -40 10 60 110 Temperature (C) 320 315 310 tRST (ms) 305 300 295 290 285 280 275 -40 10 60 110 Temperature (C) 4.75V 5.5V 5.0V FIGURE 2-25: VDD Falling to Reset Propagation Delay (tRPD) vs. Temperature (TC1270AL, TC1270ANL, TC1271AL - 4.50V min. / 4.63V typ. / 4.75V max.). 55 54 53 52 51 50 49 48 -40 10 60 110 Temperature (C) tRPD (s) FIGURE 2-28: Reset Timeout Period (tRST) vs. Temperature (TC1270AL, TC1270ANL, TC1271AL - 4.50V min. / 4.63V typ. / 4.75V max.). 325 320 315 310 305 300 295 290 285 280 275 -40 10 60 3.2V 3.15 4.0V 4.5V 5.0V 5.5V tRST (ms) tRPD (s) 110 Temperature (C) FIGURE 2-26: VDD Falling to Reset Propagation Delay (tRPD) vs. Temperature (TC1270AT, TC1270ANT, TC1271AT - 3.00V min. / 3.08V typ. / 3.15V max.). 55 54 53 52 51 50 49 48 -40 10 60 110 Temperature (C) FIGURE 2-29: Reset Timeout Period (tRST) vs. Temperature (TC1270AT, TC1270ANT, TC1271AT - 3.00V min. / 3.08V typ. / 3.15V max.). 320 315 310 tRST (ms) 305 300 295 290 285 280 275 -40 10 60 110 4.0V 2.8V 5.5V 4.5V 5.0V 3.0V tRPD (s) Temperature (C) FIGURE 2-27: VDD Falling to Reset Propagation Delay (tRPD) vs. Temperature (TC1270AR, TC1270ANR, TC1271AR - 2.55V min. / 2.63V typ. / 2.70V max.). FIGURE 2-30: Reset Timeout Period (tRST) vs. Temperature (TC1270AR, TC1270ANR, TC1271AR - 2.55V min. / 2.63V typ. / 2.70V max.). (c) 2007 Microchip Technology Inc. DS22035B-page 11 TC1270A/70AN/71A Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = -40C to +125C. 40 39 2.5 2.45 2.4 tRST (ms) tRST (ms) 38 37 36 35 34 -40 10 60 Temperature (C) 110 4.75V 5.5V 5.0V 2.35 2.3 2.25 2.2 2.15 2.1 -40 10 60 110 Temperature (C) 4.75V 5.5V 5.0V FIGURE 2-31: Reset Timeout Period (tRST) (C timeout option) vs. Temperature (TC1270AL, TC1270ANL, TC1271AL - 4.50V min. / 4.63V typ. / 4.75V max.). 40 39 tRST (ms) 38 37 36 35 34 -40 10 60 110 Temperature (C) 4.0V 4.5V 5.0V 5.5V 3.2V 3.15V FIGURE 2-34: Reset Timeout Period (tRST) (B timeout option) vs. Temperature (TC1270AL, TC1270ANL, TC1271AL - 4.50V min. / 4.63V typ. / 4.75V max.). 2.5 2.45 2.4 tRST (ms) 2.35 2.3 2.25 2.2 2.15 2.1 -40 10 60 110 Temperature (C) 4.5V 5.0V 5.5V 3.15V 4.0V 3.2V FIGURE 2-32: Reset Timeout Period (tRST) (C timeout option) vs. Temperature (TC1270AT, TC1270ANT, TC1271AT - 3.00V min. / 3.08V typ. / 3.15V max.). 40 3.0V FIGURE 2-35: Reset Timeout Period (tRST) (B timeout option) vs. Temperature (TC1270AT, TC1270ANT, TC1271AT - 3.00V min. / 3.08V typ. / 3.15V max.). 2.5 2.45 2.4 2.35 2.3 2.25 2.2 2.15 2.1 4.0V 5.0V 2.8V 5.5V 4.5V 3.0V 39 tRST (ms) tRST (ms) 38 37 36 35 4.0V 2.8V 5.5V 4.5V 5.0V 34 -40 10 60 110 Temperature (C) -40 10 60 110 Temperature (C) FIGURE 2-33: Reset Timeout Period (tRST) (C timeout option) vs. Temperature (TC1270AR, TC1270ANR, TC1271AR - 2.55V min. / 2.63V typ. / 2.70V max.). FIGURE 2-36: Reset Timeout Period (tRST) (B timeout option) vs. Temperature (TC1270AR, TC1270ANR, TC1271AR - 2.55V min. / 2.63V typ. / 2.70V max.). DS22035B-page 12 (c) 2007 Microchip Technology Inc. TC1270A/70AN/71A Note: Unless otherwise indicated, all limits are specified for VDD = 1V to 5.5V, TA = -40C to +125C. 0.22 Transient Duration (s) 0.21 tMD (s) 0.2 4.75V 4.8V 60 50 40 30 20 10 Below Line, No Reset Occurs 4.63V Above Line, Reset Occurs 2.63V 3.08V 0.19 0.18 5.5V 5.0V 0.17 -40 10 60 110 Temperature (C) 0 0.001 0.01 0.1 VTRIPMIN - VDD (V) 1 10 FIGURE 2-37: MR Low to Reset Propagation Delay (tMD) vs. Temperature (TC1270AL, TC1270ANL, TC1271AL - 4.50V min. / 4.63V typ. / 4.75V max.). 0.22 FIGURE 2-40: VDD Transient Duration vs. Reset Threshold Overdrive (VTRIP (minimum) - VDD). 1.E-02 Leakage Current (A) 1.E-04 1.E-06 +125C 13.5V 0.21 tMD (s) 0.2 4.0V 4.5V 5.5V 0.19 5.0V 1.E-08 1.E-10 1.E-12 1.E-14 +25C -40C 0.18 0.17 -40 10 60 110 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Temperature (C) Output Voltage (V) FIGURE 2-38: MR Low to Reset Propagation Delay (tMD) vs. Temperature (TC1270AT, TC1270ANT, TC1271AT - 3.00V min. / 3.08V typ. / 3.15V max.). 0.22 0.21 4.0V FIGURE 2-41: Open-Drain Leakage Current vs. Voltage Applied to RST Pin (TC1270AR, TC1270ANR, TC1271AR - 2.55V minimum). tMD (s) 0.2 0.19 5.0V 4.5V 0.18 0.17 -40 5.5V 10 60 110 Temperature (C) FIGURE 2-39: MR Low to Reset Propagation Delay (tMD) vs. Temperature (TC1270AR, TC1270ANR, TC1271AR - 2.55V min. / 2.63V typ. / 2.70V max.). (c) 2007 Microchip Technology Inc. DS22035B-page 13 TC1270A/70AN/71A 3.0 PIN DESCRIPTIONS PINOUT DESCRIPTION Pin Number TC1270A (Push-Pull, active low) SOT-143-4 SOT-23-5 TC1270AN (Open-Drain, active low) SOT-23-5 TC1271A (Push-Pull, active high) SOT-143-4 SOT-23-5 Pin Sym Type Buffer / Driver Power Ground PushPull Reset output (Push Pull), active low H = VDD > VTRIP, Reset pin is inactive (after Reset Timer Delay completes) L = VDD < VTRIP, Reset pin is active Goes active (Low) if one of these conditions occurs: 1. If VDD falls below the selected Reset voltage threshold. 2. If the MR pin is forced low. 3. During power-up. -- -- 4 -- -- RST O Open- Reset output (Open-Drain), active low Drain Float = VDD > VTRIP, Reset pin is inactive (after Reset Timer Delay completes) L = VDD < VTRIP, Reset pin is active Goes active (Low) if one of these conditions occurs: 1. If VDD falls below the selected Reset voltage threshold. 2. If the MR pin is forced low. 3. During power-up. -- -- -- 4 2 RST O PushPull Reset output (Push Pull), active high H = VDD < VTRIP, Reset pin is active L = VDD > VTRIP, Reset pin is inactive (after Reset Timer Delay completes) Goes active (High) if one of these conditions occurs: 1. If VDD falls below the selected Reset voltage threshold. 2. If the MR pin is forced low. 3. During power-up. Note 1: The MR pin has an internal weak pull-up (18.5 k typical). Standard Function The descriptions of the pins are listed in Table 3-1. TABLE 3-1: 5 4 1 2 -- 5 -- 1 -- VSS RST -- O DS22035B-page 14 (c) 2007 Microchip Technology Inc. TC1270A/70AN/71A TABLE 3-1: PINOUT DESCRIPTION (CONTINUED) Pin Number TC1270A (Push-Pull, active low) SOT-143-4 SOT-23-5 TC1270AN (Open-Drain, active low) SOT-23-5 TC1271A (Push-Pull, active high) SOT-143-4 SOT-23-5 Pin Sym Type Buffer / Driver ST (1) Manual Reset input pin This input allows a push button switch to be directly connected to the TC1270A/70AN/71A's MR pin, which can then be used to force a system Reset. The input filter (ignores) noise pulses that occur on the MR pin. H = Switch is open (internal pull-up resistor pulls signal high). State of the RST/RST pin determined by other system conditions. L = Switch is depressed (shorted to ground). This forces the RST/RST pin Active. Standard Function 3 3 -- 3 3 MR I 2 1 Note 1: 4 -- -- -- 2 1 4 -- VDD NC -- -- Power Supply Voltage -- No Connection The MR pin has an internal weak pull-up (18.5 k typical). (c) 2007 Microchip Technology Inc. DS22035B-page 15 TC1270A/70AN/71A 3.1 Ground Terminal (VSS) 3.4 Manual Reset Input (MR) VSS provides the negative reference for the analog input voltage. Typically, the circuit ground is used. The Manual Reset (MR) input pin allows a push button switch to easily be connected to the system. When the push button is depressed, it forces a system Reset. This pin has circuitry that filters noise that may be present on the MR signal. The MR pin is active-low and has an internal pull-up resistor. 3.2 Supply Voltage (VDD) VDD can be used for power supply monitoring or a voltage level that requires monitoring. 3.3 1. 2. 3. Reset Output (RST and RST) Push-Pull active-low Reset Push-Pull active-high Reset Open-Drain active-low Reset, External pull-up resistor required. There are three types of Reset output pins. These are: 3.3.1 ACTIVE-LOW (RST) - PUSH-PULL The RST push-pull output remains low while VDD is below the reset voltage threshold (VTRIP). The time that the RST pin is held low after the device voltage (VDD) returns to a high level (> VTRIP) is typically 280 ms. After the Reset delay timer expires, the RST pin will be driven to the high state. 3.3.2 ACTIVE-HIGH (RST) - PUSH-PULL The RST push-pull output remains high while VDD is below the reset voltage threshold (VTRIP). The time that the RST pin is held high after the device voltage (VDD) returns to a high level (> VTRIP) is typically 280 ms. After the Reset delay timer expires, the RST pin will be driven to the low state. 3.3.3 ACTIVE-LOW (RST) - OPEN-DRAIN The RST open-drain output remains low while VDD is below the reset voltage threshold (VTRIP). The time that the RST pin is held low after the device voltage (VDD) returns to a high level (> VTRIP) depends on the Reset Timeout selected. After the Reset Delay Timer expires, the RST pin will float. DS22035B-page 16 (c) 2007 Microchip Technology Inc. TC1270A/70AN/71A 4.0 4.1 DEVICE OPERATION General Description Figure 4-2 shows a typical circuit for a push-pull device and Figure 4-3 shows a typical circuit for an open-drain device. For many of today's microcontroller applications, care must be taken to prevent low-power conditions that can cause many different system problems. The most common causes are brown-out conditions, where the system supply drops below the operating level momentarily. The second most common cause is when a slowly decaying power supply causes the microcontroller to begin executing instructions without sufficient voltage to sustain volatile memory (RAM), thus producing indeterminate results. The TC127XA family (TC1270A, TC1270AN, and TC1271A) are cost-effective voltage supervisor devices designed to keep a microcontroller in Reset until the system voltage has reached and stabilized at the proper level for reliable system operation. These devices also operate as protection from brown-out conditions when the system supply voltage drops below a safe operating level. A Manual Reset input (MR pin) is provided. This allows a push button switch to be directly connected to the TC127XA device, and is suitable for use as a push button Reset. This allows the system to easily be reset from the external control of the push button switch. No external components are required. The Reset pin (RST or RST) will be forced active, if any of the following occur: * During device power up * VDD goes below the device threshold voltage * The Manual Reset input (MR) goes low Figure 4-1 shows a high level block diagram of the devices. The device can be described with three functional blocks. These are: * Voltage Detect circuit * Manual Reset with Glitch Filter circuit * Reset Generator circuit The Reset Generator circuit controls the reset delay time of the reset output signal. There are three Reset Delay time options. Depending on the option, the reset signal (RST/RST pin) will be held active for a minimum of 1.09 ms, 17.5 ms, or 140 ms. The TC1271A has an active-high RST output while the TC1270A and TC1270AN have an active-low RST output. The TC1270A and TC1271A have a push-pull output driver, while the TC1270AN has an open-drain output. VDD Voltage Detector Circuit Manual Reset with Glitch Filter Circuit VRST Reset Generator Circuit MRRST RST or RST MR FIGURE 4-1: Diagram. VDD 0.1 F TC127XA High Level Block VDD TC1270A/1A MR VSS RST or RST VDD Reset Input VSS Push Button FIGURE 4-2: Typical Push-Pull Application Circuit. VDD 0.1 F VDD TC1270AN Push Button MR RST VSS Reset Input VSS VDD FIGURE 4-3: Typical Open-Drain Application Circuit. The TC1270A and TC1271A devices are available in a 4-Pin SOT-143 package to maintain footprint compatibility with the TC1270, TC1271, TCM811, and TCM812 devices, and the SOT-23-5 package. The TC1270AN is only available in the SOT-23-5 package. Low supply current makes these devices suitable for battery powered applications. Device specific block diagrams are shown in Figure 4-4 through Figure 4-6. (c) 2007 Microchip Technology Inc. DS22035B-page 17 TC1270A/70AN/71A VDD Comparator + - Reference Voltage Noise Filter Output Driver (PushPull) Delay 4.2 Voltage Detect Circuit RST The Voltage Detect Circuit monitors VDD. The device's Reset voltage trip point (VTRIP) is selected when the device is ordered. The voltage on the device's VDD pin determines the output state of the RST/RST pin. VDD voltages above the VTRIP(MAX) force the RST/RST pin inactive. VDD voltages below the VTRIP(MIN) force the RST/RST pin active. The state of the RST/RST pin is unknown for VDD voltages between VTRIP(MAX) and VTRIP(MIN). This is shown in Table 4-1 MR FIGURE 4-4: TC1270A Block Diagram. VDD TABLE 4-1: VDD LEVELS TO RST/RST OUTPUT STATES Output State VDD Voltage Level Comparator + - Reference Voltage Noise Filter VSS Output Driver (OpenDrain) Delay RST VDD VTRIP(MAX) VTRIP(MIN) < VDD < VTRIP(MAX) VDD VTRIP(MIN) RST H (1, 2) RST L (1) U H U L MR Legend: H = Driven High L = Driven Low U = Unknown, driven either High or Low Note 1: The RST/RST pin will be driven inactive after the Reset Delay Timer (tRST) times out. The TC1270AN RST pin will be floated after the Reset Delay Timer (tRST) times out. FIGURE 4-5: TC1270AN Block Diagram. VDD Comparator 2: + - Reference Voltage Noise Filter Output Driver (PushPull) Delay The term VTRIP will be used as the general term for the trip point voltage where the device actually trips. RST In the case where VDD is falling (for voltages starting above VTRIP(MAX)): * Voltages above VTRIP(MAX) will never cause the RST/RST output pin to be driven Active. * Voltages below VTRIP(MIN) will always cause the RST/RST output pin to be driven Active. Now in the case where VDD is rising (for voltages starting below VTRIP(MIN)): * Voltages above VTRIP(MAX) will always cause the RST/RST output pin to be driven Inactive, (or floated - TC1270AN) after the Reset Delay Timer (tRST), times out. MR FIGURE 4-6: TC1271A Block Diagram. DS22035B-page 18 (c) 2007 Microchip Technology Inc. TC1270A/70AN/71A Table 4-2 shows the various device trip point options and their VTRIP(MAX) and VTRIP(MIN) voltages. Also the negative percentage change from common regulated voltages is shown. In the case where VDD is falling from the regulated voltage, as the VDD crosses the VTRIP voltage the RST/RST pin is driven active. Now the desired circuitry is in reset, or the circuitry has the indication that the VDD is below the selected VTRIP. In the case where VDD is rising. As the VDD crosses the VTRIP voltage, the RST/RST pin is driven inactive after the Reset Delay Timer elapses. Now the desired circuitry is released from reset and will start to operate in its normal mode, or the circuitry has the indication that the VDD is above the selected VTRIP. 4.2.1 HYSTERESIS There is also a minimal hysteresis (VHYS) on the trip point. This is so that small noise signals on the device voltage (VDD) do not cause the Reset pin (RST/RST) to "jitter" (change between driving an active and inactive). The characterization graphs shown in Figures 2-13 through 2-15 shows the device hysteresis as a percentage of the voltage trip point (VTRIP). The Reset Delay Timer (tRST) gives a time based hysteresis for the system. 4.2.2 POWER-UP/RISING VDD As the device VDD rises, the device's Reset circuit will remain active until the voltage rises above the "actual" trip point (VTRIP). Figure 4-7 shows a power-up sequence and the waveform of the RST and RST pins. As the device powers up, the voltage will start below the valid operating voltage of the device. At this voltage, the RST/RST output is not valid. Once the voltage is above the minimum operating voltage (1V) and below the selected VTRIP, the Reset output will be active. Once the device voltage rises above the VTRIP voltage, the Reset delay timer (tRST) starts. When the Reset delay timer times out, the Reset output (RST/RST) is driven inactive. VTRIP VDD 1V tRST(1) TABLE 4-2: SELECTING THE TRIP POINT - % From Regulated Voltage 5.0V 5.0% 10.0% 10.0% 15.0% -- -- -- -- -- -- 3.3V -- -- -- -- 4.5% 9.2% 9.2% 13.7% -- -- 3.0V -- -- -- -- -- -- -- -- 10.0% 15.0% Trip VTRIP(MAX)(1) Voltage / Selection VTRIP(MIN)(2) L M T S R Note 1: 4.75V 4.50V 4.50V 4.25V 3.15V 3.00V 3.00V 2.85V 2.70V 2.55V 2: Voltage regulator circuit must have tighter tolerance (%) than VTRIP(MAX) % from regulated voltage. Circuitry being reset must have a wider tolerance (%) than VTRIP(MIN) % from regulated voltage. RST(2) RST Note 1: Additional system current is consumed during the tRST time. 2: The TC1270AN requires an external pull-up resistor. The TC1270A/TC1270AN/TC1271A devices are optimized to reject fast transient glitches on the VDD line. If the low input signal (which is below VTRIP) is not rejected, the Reset output is driven active within 50 s of VDD falling through the Reset voltage threshold. After the device exits the Reset condition, the delay circuitry will hold the RST/RST pin active until the appropriate Reset delay time (tRST) has elapsed. During device power up, the input voltage is below the Trip Point voltage. The device must enter the valid operating range for the device to start operation. FIGURE 4-7: Power-up. RST/RST pin Operation (c) 2007 Microchip Technology Inc. DS22035B-page 19 TC1270A/70AN/71A 4.2.3 POWER-DOWN/BROWN-OUTS As the device powers-down/brown-outs, the VDD falls from a voltage above the devices trip point (VTRIP). The device will trip at a voltage between the maximum trip point (VTRIP(MAX)) and the minimum trip point (VTRIP(MIN)). Once the device voltage (VDD) goes below this voltage, the RST/RST pin will be forced to the active state. Figure 4-8 shows the waveform of the RST pin as determined by the VDD voltage. As the VDD voltage falls from the normal operating point, the device "enters" reset by crossing the VTRIP voltage (between VTRIP(MAX) and VTRIP(MIN)). Then when VDD voltage rises, the device "exits" reset by crossing the VTRIP voltage (below or at VTRIP(MAX)). After the "exit" state has been detected, the Reset Delay Timer (tRST) starts. Once the tRST time completes, the Reset pin is driven inactive. Table 4-3 shows the state of the RST or RST pins. TABLE 4-3: Device RESET PIN STATES State of RST Pin when: VDD < VTRIP VDD > VTRIP (1) H -- State of RST Pin when: VDD < VTRIP -- H VDD > VTRIP (1) -- L Output Driver Push-Pull Push-Pull TC1270A TC1271A Note 1: L -- The RST/RST pin will be driven inactive after the Reset Delay Timer (tRST) times out. VDD VTRIP (with VDD Falling) 1V RST(1) tRD Note 1: VTRIP (with VDD Rising) tRST < 1V is outside the device specifications tRD tRST The TC1270AN requires an external pull-up resistor. FIGURE 4-8: RST Operation as determined by the VTRIP. DS22035B-page 20 (c) 2007 Microchip Technology Inc. TC1270A/70AN/71A 4.3 Negative Going VDD Transients 4.4 The minimum pulse width (time) required to cause a Reset may be an important criteria in the implementation of a Power-on Reset (POR) circuit. This time is referred to as transient duration. The TC127XA devices are designed to reject a level of negative-going transients (glitches) on the power supply line. Transient duration is the amount of time needed for these supervisory devices to respond to a drop in VDD. The transient duration time (tTRAN) is dependent on the magnitude of VTRIP - VDD (overdrive). Any combination of duration and overdrive that lies under the duration/overdrive curve will not generate a Reset signal. Generally speaking, the transient duration time decreases with an increase in the VTRIP - VDD voltage. Figure 4-9 shows an example transient duration vs. Reset comparator overdrive. It shows that the farther below the trip point the transient pulse goes, the duration of the pulse required to cause a Reset gets shorter. So any combination of duration and overdrive that lays under the curve will not generate a Reset signal. Combinations above the curve are detected as a brown-out or power-down. Transient immunity can be improved by adding a bypass capacitor (typically 0.1 F) as close as possible to the VDD pin of the TC127XA device. Manual Reset with Glitch Filter Circuit The Manual Reset input pin (MR) allows the Reset pins (RST/RST) to be manually forced to their active states. The MR pin has circuitry to filter noise pulses that may be present on the pin. Figure 4-10 shows a block diagram for using the TC127XA with a push button switch. To minimize the required external components, the MR input has an internal pull-up resistor. A mechanical push button or active logic signal can drive the MR input. Once MR has been low for a time, tMD (the Manual Reset delay time), the Reset output pins are forced active. The Reset output pins will remain in their active states for the Reset delay timer time out period (tRST). Figure 4-11 shows a waveform for the Manual Reset switch input and the Reset pins output. +5V VDD MR TC127XA RST VSS PIC(R) MCU MCLR 5V Supply Voltage VTRIP(MIN) - VDD (Overdrive) tTRAN (Duration) Time (s) VTRIP(MAX) VTRIP(MIN) FIGURE 4-10: Push Button Reset. tMR 0V MR Transient Duration (ms) Area above curve will generate a reset signal RST RST tMD VIH VIL tRST Area below curve will not generate a reset signal Transient Overdrive Voltage (mV) The MR input typically ignores input pulses of 100 ns. FIGURE 4-9: Example of Typical Transient Duration Waveform. FIGURE 4-11: 4.4.1 MR Input - Push Button. NOISE FILTER The noise filter filters out noise spikes (glitches) on the Manual Reset pin (MR). Noise spikes less than 100 ns (typical) are filtered. (c) 2007 Microchip Technology Inc. DS22035B-page 21 TC1270A/70AN/71A 4.5 Reset Generator Circuit 4.5.2 The output signals from the Voltage Detect Circuit and the Manual Reset with Glitch Filter Circuit are OR'd together and is used to activate the Reset Generator Module. After the reset conditions have been removed (the MR pin is no longer forced low and the input voltage is greater than the Trip Point voltage), the Reset Generator circuit determines the reset delay timeout required. There are three options for the delay circuit. These are: * 2.19 ms (typical) delay * 35 ms (typical) delay * 280 ms (typical) delay EFFECT OF TEMPERATURE ON RESET POWER-UP TIMER (tRPU) The Reset delay timer time out period (tRST) determines how long the device remains in the Reset condition. This time out is affected by both the device VDD and temperature. Typical responses for different VDD values and temperatures are shown in Figures 2-28, 2-29 and 2-30. TABLE 4-4: RESET DELAY TIMER TIME OUTS tRST Units Max 4.38 70 560 This is the maximum time that the Reset Delay Timer will "hold" the Reset pin active after VDD rises above VTRIP ms ms ms Min 1.09 17.5 140 This is the minimum time that the Reset Delay Timer will "hold" the Reset pin active after VDD rises above VTRIP Note 1: VDD VTRIP RST Typ 2.19 35 280 4.5.1 RESET DELAY TIMER The Reset delay timer ensures that the TC127XA device will "hold" the embedded system in Reset until the system voltage has stabilized. The Reset delay timer time out is shown in Table 4-4. The Reset Delay Timer starts once the Voltage Detector Circuit output AND the Manual Reset with Glitch Filter Circuit output become inactive. While the Reset Delay Timer is active, the RST or RST pin is driven to the active state. Once the Reset Delay Timer times-out, the RST or RST pin is driven inactive. The Reset delay timer (tRST) starts after the device voltage rises above the "actual" trip point (VTRIP). When the Reset delay timer times out, the Reset output pin (RST/RST) is driven inactive. The Reset Delay Timer is cleared, if either (or both) the Voltage Detector Circuit output OR the Manual Reset with Glitch Filter Circuit output become active. The RST or RST pin continues to be driven to the active state. Figure 4-12 illustrates when the Reset Delay Timer (tRST) is active or inactive. Shaded rows are custom ordered time outs. tRST Reset Delay Timer Active Reset Delay Timer Inactive Reset Delay Timer Inactive See Figures 2-9, 2-7 and 2-8 See Figures 2-9, 2-7 and 2-8 See Figures 2-12, 2-11 and 2-10 FIGURE 4-12: Waveform. Reset Power-up Timer DS22035B-page 22 (c) 2007 Microchip Technology Inc. TC1270A/70AN/71A 5.0 APPLICATION INFORMATION 5.3 Note: This section shows application related information that may be useful for your particular design requirements. Using in PIC(R) Microcontroller, ICSPTM Applications This operation can only be done using the device with the Open-Drain RST pin (TC1270AN). 5.1 Supply Monitor Noise Sensitivity The TC127XA devices are optimized for fast response to negative-going changes in VDD. Systems with an inordinate amount of electrical noise on VDD (such as systems using relays) may require a 0.01 F or 0.1 F bypass capacitor to reduce detection sensitivity. This capacitor should be installed as close to the TC127XA as possible to keep the capacitor lead length short. Figure 5-4 shows the typical application circuit for using the TC1270AN for voltage supervisory function when the PIC microcontroller will be programmed via the In-Circuit Serial ProgrammingTM (ICSPTM) feature. Additional information is available in TB087, "Using Voltage Supervisors with PICmicro(R) Microcontroller Systems which Implement In-Circuit Serial ProgrammingTM", DS91087. Note: It is recommended that the current into the RST pin be current limited by a 1 k resistor. VDD/VPP 0.1 F VDD RPU VDD PIC(R) Microcontroller MCLR Reset input) (Active-Low) VSS 0.1 F VDD TC127XA MR VSS RST RST TC1270AN FIGURE 5-1: Typical Application Circuit with Bypass Capacitor. RST VSS 1 k 5.2 Conventional Voltage Monitoring Figure 5-2 and Figure 5-3 show the TC127XA in conventional voltage monitoring applications. + - VDD FIGURE 5-4: Typical Application Circuit for PIC(R) Microcontroller with the ICSPTM Feature. RST BATLOW TC127XA VSS FIGURE 5-2: Battery Voltage Monitor. VDD + Pwr Sply - VSS RST TC127XA Power Good FIGURE 5-3: Power Good Monitor. (c) 2007 Microchip Technology Inc. DS22035B-page 23 TC1270A/70AN/71A 5.4 Modifying The Trip Point, VTRIP 5.5 MOSFET Low-Drive Protection Although the TC127XA device has a fixed voltage trip point (VTRIP), it is sometimes necessary to make custom adjustments. This can be accomplished by connecting an external resistor divider to the TC127XA VDD pin. This causes the VSOURCE voltage to be at a higher voltage than when the TC127XA input equals it's VTRIP voltage (Figure 5-5). To maintain detector accuracy, the bleeder current through the divider should be significantly higher than the 15 A maximum operating current required by the TC127XA. A reasonable value for this bleeder current is 1 mA (67 times the 10 A required by the TC127XA). For example, if VTRIP = 2V and the desired trip point is 2.5V, the value of R1 + R2 is 2.5 k (2.5V/1 mA). The value of R1 + R2 can be rounded to the nearest standard value and plugged into the equation of Figure 5-5 to calculate values for R1 and R2. 1% tolerance resistors are recommended. VSOURCE Note 1: R2 VDD RST or RST Low operating power and small physical size make the TC1270AN series ideal for many voltage detector applications. Figure 5-6 shows a low-voltage gate drive protection circuit that prevents overheating of the logic-level MOSFET due to insufficient gate voltage. When the input signal is below the threshold of the TC1270AN, its output grounds the gate of the MOSFET. VTRIP 270 (1) VDD RL VDD RST TC1270AN VSS MTP3055EL This resistance needs to be properly sized for the selected Trip point voltage related to the VOL operation. TC127XA R1 VSS FIGURE 5-6: Protection. MOSFET Low-Drive V Where: ------------------x R +1R SOURCE 1 R =V 2 TRIP VSOURCE = Voltage to be monitored VTRIP = Threshold Voltage setting Note: In this example, VSOURCE must be greater than (VTRIP). FIGURE 5-5: Modify Trip-Point using External Resistor Divider. DS22035B-page 24 (c) 2007 Microchip Technology Inc. TC1270A/70AN/71A 5.6 Controllers and Processors With Bidirectional I/O Pins 5.8 Reset Signal Integrity During Power-Down Some microcontrollers have bidirectional Reset pins. Depending on the current drive capability of the controller pin, an indeterminate logic level may result if there is a logic conflict. This can be avoided by adding a 4.7 k resistor in series with the output of the TC127XA (Figure 5-7). If there are other components in the system that require a Reset signal, they should be buffered so as not to load the Reset line. If the other components are required to follow the Reset I/O of the microcontroller, the buffer should be connected as shown with the solid line. Buffered Reset to system VDD The TC1270A and TC1271A reset output is valid down to VDD = 1.0V. Below this voltage the output becomes an "open circuit" and does not sink current. This means CMOS logic inputs to the Microcontroller will be floating at an undetermined voltage. Most digital systems are completely shut down well above this voltage. However, in situations where the Reset signal must be maintained valid to VDD = 0V, external circuitry is required. For devices where the Reset signal is active-low, a pull-down resistor must be connected from the TC1270A RST pin to ground to discharge stray capacitances and hold the output low (Figure 5-9). Similarly for devices where the Reset signal is active-high, a pull-up resistor to VDD is required to ensure a valid high RST signal for VDD below 1.0V (Figure 5-10). This resistor value, though not critical, should be chosen such that it does not appreciably load the Reset pin under normal operation (100 k will be suitable for most applications). VDD VDD VDD VDD TC1270A/71A MR VSS RST or RST Reset I/O 4.7 k VSS FIGURE 5-7: Interfacing the TC1270A or TC1271A Push-Pull Output to a Bidirectional Reset I/O pin. TC1270A MR VSS RST R1 100 k 5.7 Migration Paths Figure 5-8 shows the 5-pin SOT-23 footprint of the TC1270A, TC1270AN and TC1271A devices. Devices that are in the 3-pin SOT-23 package could be used in that circuit with the loss of the Manual Reset functionality. Examples of compatible footprint devices in the SOT-23-3 package are the MCP111, MCP112, TC54, and TC51 devices. This allows the system to be designed to offer a "base" functionality and a higher end system with the "enhanced" functionality, which includes a manual reset. SOT-23-5 NC VDD MR 1 2 3 4 5 VSS RST or RST VDD 3 1 SOT-23-3 2 VSS RST or RST FIGURE 5-9: Ensuring a valid active-low Reset pin output state as VDD approaches 0V. VDD VDD TC1271A MR VSS RST R1 100 k FIGURE 5-10: Ensuring a valid active-high Reset pin output state as VDD approaches 0V. FIGURE 5-8: Comparison. SOT-23 5-pin to 3-pin (c) 2007 Microchip Technology Inc. DS22035B-page 25 TC1270A/70AN/71A 6.0 STANDARD DEVICES The configuration includes the: * Voltage Trip Point (VTRIP) * Reset Time Out (tRST) Table 6-1 shows the standard devices and their order number that are available and their respective configuration. TABLE 6-1: Minimum STANDARD VERSIONS Reset Threshold (V) Maximum Typical Code Reset Time Out (ms) Maximum Minimum Code (1) Typical Package Order Number Replaces Device SOT-23-5 TC1270A 4.50 4.63 4.75 L 140 280 560 "blank" SOT-143 SOT-23-5 TC1270A 4.25 4.38 4.50 M 140 280 560 "blank" SOT-143 SOT-23-5 TC1270A 3.00 3.08 3.15 T 140 280 560 "blank" SOT-143 SOT-23-5 TC1270A 2.85 2.93 3.00 S 140 280 560 "blank" SOT-143 SOT-23-5 TC1270A TC1270AN TC1270AN TC1270AN TC1270AN TC1270AN TC1271A 2.55 2.63 2.70 R 4.50 4.63 4.75 3.00 3.08 3.15 L T 140 140 140 140 140 140 140 280 280 280 280 280 280 280 560 560 560 560 560 560 560 "blank" SOT-143 TC1270ALVCTTR TC1270ALVRCTR -- TC1270LERC / TCM811LERC TC1270AMVCTTR -- TC1270AMVRCTR TC1270MERC / TCM811MERC TC1270ATVCTTR TC1270ATVRCTR TC1270ASVCTTR TC1270ASVRCTR TC1270ARVCTTR TC1270ARVRCTR TC1270ANLVCT TC1270ANMVCT TC1270ANTVCT TC1270ANSVCT TC1270ANRVCT TC1271ALVCTTR TC1271ALVRCTR -- TC1270TERC / TCM811TERC -- TC1270SERC / TCM811SERC -- TC1270RERC / TCM811RERC -- -- -- -- -- -- TC1271LERC / TCM812LERC "blank" SOT-23-5 "blank" SOT-23-5 "blank" SOT-23-5 "blank" SOT-23-5 "blank" SOT-23-5 SOT-23-5 "blank" 4.25 4.38 4.50 M 2.85 2.93 3.00 S 2.55 2.63 2.70 R 4.50 4.63 4.75 L SOT-143 SOT-23-5 TC1271AMVCTTR -- TC1271AMVRCTR TC1271MERC / TCM812MERC TC1271ATVCTTR TC1271ATVRCTR TC1271ASVCTTR TC1271ASVRCTR TC1271ARVCTTR TC1271ARVRCTR -- TC1271TERC / TCM812TERC -- TC1271SERC / TCM812SERC -- TC1271RERC / TCM812RERC TC1271A 4.25 4.38 4.50 M 140 280 560 "blank" SOT-143 SOT-23-5 TC1271A 3.00 3.08 3.15 T 140 280 560 "blank" SOT-143 SOT-23-5 TC1271A 2.85 2.93 3.00 S 140 280 560 "blank" SOT-143 SOT-23-5 TC1271A Note 1: 2.55 2.63 2.70 R 140 280 560 "blank" SOT-143 "A" timeout delay options are only standard in the SOT-23-5 package. SOT-143 package is a custom request. DS22035B-page 26 (c) 2007 Microchip Technology Inc. TC1270A/70AN/71A 7.0 CUSTOM CONFIGURATIONS The following Custom Reset Trip Point is available (see Table 7-1). TABLE 7-1: Trip Voltage Selection (1) CUSTOM TRIP POINT VTRIP(MAX) / VTRIP(MIN) 2.85V 2.70V - % From Regulated Voltage 3.0V 5.0% 10.0% Note 1: Contact factory for additional information. Table 7-2 shows the codes that specify the desired Reset time out (tRST) for custom devices TABLE 7-2: Code B C "blank" Note 1: DELAY TIME OUT ORDERING CODES Reset Delay Comment Time (Typ) (ms) 2.19 35 280 Note 1 Note 1 Delay timings for standard device offerings This delay timing option is not the standard offering. For information on ordering devices with these delay times, contact your local Microchip sales office. Minimum purchase volumes are required. (c) 2007 Microchip Technology Inc. DS22035B-page 27 TC1270A/70AN/71A 8.0 8.1 DEVELOPMENT TOOLS Evaluation/Demonstration Boards The SOIC14-EV (102-00094) board has a SOT-23-6 footprint, that can be jumpered into any portion of the circuit. This will allow any footprint that the TC1270A requires in the SOT-23-5 package. The SOT-23-5/6 Evaluation Board (VSUPEV2) can be used to evaluate the characteristics of the TC127XA devices. This blank PCB has footprints for: * * * * Pull-up Resistor Pull-down Resistor Loading Capacitor In-line Resistor There is also a power supply filtering capacitor. For evaluating the TC127XA devices, the selected device should be installed into the Option A footprint. FIGURE 8-2: (SOIC14EV). SOIC-14 Evaluation Board These boards may be purchased directly from the Microchip web site at www.microchip.com. FIGURE 8-1: SOT-23-5/6 Voltage Supervisor Evaluation Board (VSUPEV2). DS22035B-page 28 (c) 2007 Microchip Technology Inc. TC1270A/70AN/71A 9.0 9.1 PACKAGING INFORMATION Package Marking Information Example: Part Number TC1270ALVCTTR TC1270AMVCTTR TC1270ATVCTTR TC1270ASVCTTR TC1270ARVCTTR TC1270ANLVCTTR TC1270ANMVCTTR TC1270ANTVCTTR TC1270ANSVCTTR TC1270ANRVCTTR 5-Pin SOT-23 Code F1NN F2NN F3NN F4NN F5NN FSNN FTNN FUNN FVNN FWNN Part Number TC1271ALVCTTR TC1271AMVCTTR TC1271ATVCTTR TC1271ASVCTTR TC1271ARVCTTR Code J1NN J2NN J3NN J4NN J5NN XXNN F125 4-Lead SOT-143 Part Number Code D1NN D2NN D3NN D4NN D5NN E1NN E2NN E3NN E4NN E5NN Example: Part Number TC1271ALVRCTR TC1271AMVRCTR TC1271ATVRCTR TC1271ASVRCTR TC1271ARVRCTR Code C1NN C2NN C3NN C4NN C5NN XXNN TC1270ALVRCTR TC1270AMVRCTR TC1270ATVRCTR TC1270ASVRCTR TC1270ARVRCTR TC1270ANLVRCTR TC1270ANMVRCTR TC1270ANTVRCTR TC1270ANSVRCTR TC1270ANRVRCTR C125 Legend: XX...X Y YY WW NN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2007 Microchip Technology Inc. DS22035B-page 29 TC1270A/70AN/71A 5-Lead Plastic Small Outline Transistor (CT) [SOT-23] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging b N E E1 1 e 2 3 e1 D A A2 c A1 L L1 Units Dimension Limits Number of Pins Lead Pitch Outside Lead Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Footprint Foot Angle Lead Thickness N e e1 A A2 A1 E E1 D L L1 c 0.90 0.89 0.00 2.20 1.30 2.70 0.10 0.35 0 0.08 MIN MILLIMETERS NOM 5 0.95 BSC 1.90 BSC - - - - - - - - - - 1.45 1.30 0.15 3.20 1.80 3.10 0.60 0.80 30 0.26 MAX Lead Width b 0.20 - 0.51 Notes: 1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side. 2. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-091B DS22035B-page 30 (c) 2007 Microchip Technology Inc. TC1270A/70AN/71A 4-Lead Plastic Small Outline Transistor (RC) [SOT-143] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D e e/2 N E E1 1 e1 2 A A2 c A1 b2 3X b L1 L Units Dimension Limits Number of Pins Pitch Lead 1 Offset Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Footprint Foot Angle Lead Thickness Lead 1 Width Leads 2, 3 & 4 Width N e e1 A A2 A1 E E1 D L L1 c b1 b 0 0.08 0.76 0.30 0.80 0.75 0.01 2.10 1.20 2.67 0.13 MIN MILLIMETERS NOM 4 1.92 BSC 0.20 BSC - 0.90 - - 1.30 2.90 0.50 0.54 REF - - - - 8 0.20 0.94 1.22 1.07 0.15 2.64 1.40 3.05 0.60 MAX 0.54 Notes: 1. Significant Characteristic. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-031B (c) 2007 Microchip Technology Inc. DS22035B-page 31 TC1270A/70AN/71A 9.2 Product Tape and Reel Specifications EMBOSSED CARRIER DIMENSIONS (8 MM TAPE ONLY) Top Cover Tape FIGURE 9-1: A0 W K0 B0 P TABLE 1: Case Outline OT RC CARRIER TAPE/CAVITY DIMENSIONS Package Type SOT-23 SOT-143 5L 4L Carrier Dimensions W mm 8 8 P mm 4 4 A0 mm 3.2 3.1 Cavity Dimensions B0 mm 3.2 2.69 K0 mm 1.4 1.3 Output Quantity Units 3000 3000 Reel Diameter in mm 180 180 FIGURE 9-2: 5-LEAD SOT-23 DEVICE TAPE AND REEL SPECIFICATIONS Device Marking User Direction of Feed Pin 1 W, Width of Carrier Tape Pin 1 P, Pitch Standard Reel Component Orientation Reverse Reel Component Orientation DS22035B-page 32 (c) 2007 Microchip Technology Inc. TC1270A/70AN/71A FIGURE 9-3: 4-LEAD SOT-143 DEVICE TAPE AND REEL SPECIFICATIONS Component Taping Orientation for 4-Pin SOT-143 Devices User Direction of Feed Device Marking W Pin 1 P Standard Reel Component Orientation for TR Suffix Device (Mark Right Side Up) Carrier Tape, Number of Components Per Reel and Reel Size: Package 4-Pin SOT-143 Carrier Width (W) 8 mm Pitch (P) 4 mm Part Per Full Reel 3000 Reel Size 7 in. (c) 2007 Microchip Technology Inc. DS22035B-page 33 TC1270A/70AN/71A NOTES: DS22035B-page 34 (c) 2007 Microchip Technology Inc. TC1270A/70AN/71A APPENDIX A: REVISION HISTORY Revision B (June 2007) * Added new options: - Open-Drain output - New Reset Delay timeouts. * Updated Package Outline Drawings * Updated Revision History * Added new options to Product Identification System Revision A (March 2007) * Original Release of this Document. (c) 2007 Microchip Technology Inc. DS22035B-page 35 TC1270A/70AN/71A NOTES: DS22035B-page 36 (c) 2007 Microchip Technology Inc. TC1270A//70AN/71A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device XX X X Range XX X Option Examples: a) TC1270ASVCTTR: 2.85V min. / 2.93V typ. / 3.00V max. voltage trip point, Push-pull active low reset, Reset Delay Timer = 280 ms, 5-LD SOT-23, Tape and Reel, -40C to +125C TC1270ALVRCTR: 4.50V min. / 4.63V typ. / 4.75V max. voltage trip point, Push-pull active low reset, Reset Delay Timer = 280 ms, 4-LD SOT-143, Tape and Reel, -40C to +125C TC1270ANMBVCTTR: 4.25V min. / 4.38V typ. / 4.50V max. Open-drain active low reset, Reset Delay Timer = 2.19 ms, 5-Lead SOT-23, Tape and Reel, -40C to +125C TC1270ANLCVCT: 4.50V min. / 4.63V typ. / 4.75V max. Open-drain active low reset, Reset Delay Timer = 35 ms, 5-Lead SOT-23, -40C to +125C TC1271ARVCTTR: 2.55V min. / 2.63V typ. / 2.70V max. voltage trip point, Push-pull active high reset, Reset Delay Timer = 280 ms, 5-LD SOT-23, Tape and Reel, -40C to +125C TC1271ATVRCTR: 3.00V min. / 3.08V typ. / 3.15V max. voltage trip point, Push-pull active high reset, Reset Delay Timer = 280 ms, 4-LD SOT-143, Tape and Reel, -40C to +125C Options VTRIP Reset Delay Temperature Package Tape/Reel Options Device: TC1270A: Voltage Supervisor with Manual Reset TC1270AN: Voltage Supervisor with Manual Reset TC1271A: Voltage Supervisor with Manual Reset R S T M L = = = = = 2.55V (min.) / 2.63V (typ.) / 2.70V (max.) 2.85V (min.) / 2.93V (typ.) / 3.00V (max.) 3.00V (min.) / 3.08V (typ.) / 3.15V (max.) 4.25V (min.) / 4.38V (typ.) / 4.50V (max.) 4.50V (min.) / 4.63V (typ.) / 4.75V (max.) b) VTRIP Options: c) Time Out Options: B = C = "blank" = tRST = 2.19 ms (typ) tRST = 35 ms (typ) tRST = 280 ms (typ) d) Temperature Range: V Package: = -40C to +125C CT = Plastic Small Outline Transistor, SOT-23, 5-lead RC = Plastic Small Outline Transistor, SOT-143, 4-lead e) TR = Tape and Reel Tape/Reel Option: f) (c) 2007 Microchip Technology Inc. DS22035B-page 37 TC1270A//70AN/71A NOTES: DS22035B-page 38 (c) 2007 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2007 Microchip Technology Inc. DS22035B-page 39 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 ASIA/PACIFIC India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 06/25/07 DS22035B-page 40 (c) 2007 Microchip Technology Inc. |
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